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intel ? 80c186ea/80c188ea and 80l186ea/80l188ea 16-bit high-integration embedded processors datasheet intel ? 80c186 upgrade for power critical applications fully static operation true cmos inputs and outputs product features the intel ? 80c186ea is a chmos high integration embedded microprocessor. the intel ? 80c186ea includes all of the features of an ``enhanced mode'' intel ? 80c186 while adding the additional capabilities of idle and powerdown modes. in numerics mode, the intel ? 80c186ea interfaces directly with an intel ? 80c187 numerics coprocessor . integrated feature set ? static 186 cpu core ? power save, idle and powerdown modes ?clock generator ? 2 independent dma channels ? 3 programmable 16-bit timers ? dynamic ram refresh control unit ? programmable memory and peripheral chip select logic ? programmable wait state generator ? local bus controller ? system-level testing support (high impedance test mode) speed versions available (3v) ?13 mhz (intel ? 80l186ea13/ 80l188ea13) direct addressing capability to 1 mbyte memoryand64kbytei/o supports intel ? 80c187 numeric coprocessor interface (intel ? 80c186ea only) available in the following packages: ? 68-pin plastic leaded chip carrier (plcc) available in extended temperature range (-40c to +85c) speed versions available (5v): ?25 mhz (intel ? 80c186ea25/80c188ea25) ?20 mhz (intel ? 80c186ea20/80c188ea20) ?13 mhz (intel ? 80c186ea13/80c188ea13) order number: 272432-005 april 2002
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties rel ating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products a re not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 80c186ea/80c188ea and 80l186ea/80l188ea may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2002 alertview, i960, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, commerce cart, ct connect, ct media, dialogic, dm3, etherexpress, etox, flashfile, gatherround, i386, i486, icat, icomp, insight960, instantip, intel, intel logo, intel386, intel486, intel74 0, inteldx2, inteldx4, intelsx2, intel chatpad, intel create&share, intel dot.station, intel gigablade, intel inbusiness, intel inside, intel insi de logo, intel netburst, intel netstructure, intel play, intel play logo, intel pocket concert, intel singledriver, intel speedstep, intel strataflash, intel te amstation, intel weboutfitter, intel xeon, intel xscale, itanium, jobanalyst, landesk, lanrover, mcs, mmx, mmx logo, netport, netportexpress, optimizer logo, overdrive, paragon, pc dads, pc parents, pentium, pentium ii xeon, pentium iii xeon, performance at your command, proshare, remoteexpress, screamline, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside, the journey inside, this way in, tokenexpress, trillium, vivonic, and vtune are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states an d other countries. *other names and brands may be claimed as the property of others.
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... .....7 2.0 intel? 80c186ea core architecture .............................................................................................9 2.1 bus interface unit ............................................................................................................ .....9 2.2 clock generator.............................................................................................................. ......9 3.0 intel? 80c186ea peripheral architecture .................................................................................11 3.1 interrupt control unit ........................................................................................................ ..11 3.2 timer/counter unit ........................................................................................................... ..11 3.3 dma control unit.............................................................................................................. ..14 3.4 chip-select unit............................................................................................................. ..... 14 3.5 refresh control unit .......................................................................................................... .14 3.6 power management............................................................................................................1 4 3.7 80c187 interface (80c186ea only) ...................................................................................15 3.8 once test mode ...............................................................................................................1 5 4.0 intel? 80c186xl and intel? 80c186ea differences .................................................................16 4.1 pinout compatibility ......................................................................................................... ... 16 4.2 operating modes .............................................................................................................. ..16 4.3 ttl vs. cmos inputs .........................................................................................................16 4.4 timing specifications........................................................................................................ ..16 4.5 package information.......................................................................................................... .17 4.6 pin descriptions............................................................................................................. ..... 17 5.0 intel? 80c186ea pinout ..............................................................................................................22 6.0 package thermal specifications ................................................................................................24 7.0 electrical specification ...............................................................................................................25 7.1 absolute maximum ratings*...............................................................................................25 7.2 recommended connections .............................................................................................. 25 8.0 dc specifications ........................................................................................................................26 8.1 icc versus frequency and voltage ................................................................................... 28 8.2 pdtmr pin delay calculation ............................................................................................29
contents 4 datasheet 9.0 ac specifications ........................................................................................................................30 10.0 ac test conditions ..................................................................................................................... 34 11.0 ac timing waveforms ................................................................................................................ 35 12.0 derating curves ........................................................................................................................... 38 13.0 reset ............................................................................................................................... .............. 39 14.0 bus cycle waveforms .................................................................................................................42 15.0 product name execution timings ............................................................................................. 49 16.0 revision history .......................................................................................................................... 56 17.0 errata ............................................................................................................................... ............. 56
datasheet 5 contents figures 1 product name block diagram ...................................................................................................... 8 2 clock configurations........................................................................................................... ........10 3 68-lead plcc pinout diagram ..................................................................................................23 4 ac test load.................................................................................................................... ..........34 5 input and output clock waveform.............................................................................................. 35 6 output delay and float waveform .............................................................................................35 7 input setup and hold ............................................................................................................. ..... 36 8 relative signal waveform ........................................................................................................ ..37 9 typical output delay variations versus load capacitance .......................................................38 10 typical rise and fall variations versus load capacitance .......................................................38 11 powerup reset waveforms ........................................................................................................ 40 12 warm reset waveforms........................................................................................................... ..41 13 read, fetch and refresh cycle waveform ................................................................................42 14 write cycle waveform ........................................................................................................... ..... 43 15 halt cycle waveform ............................................................................................................ ......44 16 inta cycle waveform ............................................................................................................ ....45 17 hold/hlda waveform............................................................................................................ ..46 18 dram refresh cycle during hold acknowledge .......................................................................47 19 ready waveform ................................................................................................................ ........48 20 instruction set summary ........................................................................................................ ....50 tables 1 peripheral control block registers.............................................................................................12 2 intel? 80c186ea slave mode peripheral control block registers ............................................ 13 3 prefix identification .......................................................................................................... ...........17 4 pin description nomenclature .................................................................................................... 18 5 pin descriptions............................................................................................................... ...........19 6 plcc pin names with package location...................................................................................22 7 plcc package location with pin names...................................................................................22 8 thermal resistance (qca) at various airflows (in c/watt) .......................................................24 9 dc specifications (80c186ea/80c188ea) ........................................................................26 10 dc specifications (80l186ea/80l188ea).......................................................................... 27 11 cdev values................................................................................................................... ...........28 12 ac characteristics?80c186ea25/80c186ea20/80c186ea13 ................................................30 13 ac characteristics?80l186ea13/80c186ea8 .........................................................................32 14 relative timings (80c186ea25/20/13, 80l186ea13)................................................................ 33
contents 6 datasheet revision history date revision description june 2002 005 discontinued device reference removal and reformatting. april 2002 004 datasheet updates
introduction product name datasheet 7 1.0 introduction unless specifically noted, all references to the intel? 80c186ea apply to the intel ? 80c188ea, intel ? 80l186ea, and intel ? 80l188ea. references to pins that differ between the intel ? 80c186ea/80l186ea and the intel ? 80c188ea/ 80l188ea are given in parentheses. the ?l? in the part number denotes low voltage operation. physically and functionally, the ?c? and ?l? devices are identical. the 80c186ea is the second product in a new generation of low-power, high-integration microprocessors. it enhances the existing intel ? 80c186xl family by offering new features and operating modes. the 80c186ea is object code compatible with the 80c186xl embedded processor. the 80l186ea is the 3v version of the 80c186ea. the 80l186ea is functionally identical to the 80c186ea embedded processor. current 80c186ea customers can easily upgrade their designs to use the 80l186ea and benefit from the reduced power consumption inherent in 3v operation. the feature set of the 80c186ea/80l186ea meets the needs of low-power, space-critical applications. low-power applications benefit from the static design of the cpu core and the integrated peripherals as well as low voltage operation. minimum current consumption is achieved by providing a powerdown mode that halts operation of the device, and freezes the clock circuits. peripheral design enhancements ensure that non-initialized peripherals consume little current. space-critical applications benefit from the integration of commonly used system peripherals. two flexible dma channels perform cpu-independent data transfers. a flexible chip select unit simplifies memory and peripheral interfacing. the interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals. three general purpose timer/counters round out the feature set of the 80c186ea. figure 1 shows a block diagram of the 80c186ea/ 80c188ea. the execution unit (eu) is an enhanced 8086 cpu core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static operation. the bus interface unit (biu) is the same as that found on the original 80c186 family products. an independent internal bus is used to allow communication between the biu and internal peripherals.
introduction 8 product name datasheet figure 1. product name block diagram note: pin names in parentheses apply to the 80c186ea / 80l188ea
intel? 80c186ea core architecture product name datasheet 9 2.0 intel ? 80c186ea core architecture 2.1 bus interface unit the 80c186ea core incorporates a bus controller that generates local bus control signals. in addition, it employs a hold/hlda protocol to share the local bus with other bus masters. the bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) information. it is also responsible for reading data off the local bus during a read operation. srdy and ardy input pins are provided to extend a bus cycle beyond the minimum four states (clocks). the local bus controller also generates a control signal (den ) when interfacing to external transceiver chips. this capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus. 2.2 clock generator the processor provides an on-chip clock generator for both internal and external clock generation. the clock generator features a crystal oscillator, a divideby- two counter, and two low-power operating modes. the oscillator circuit is designed to be used with either a parallel resonant fundamental or third- overtone mode crystal network. alternatively, the oscillator circuit may be driven from an external clock source. figure 2 shows the various operating modes of the oscillator circuit. the crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. this counter is used to drive all internal phase clocks and the external clkout signal. clkout is a 50% duty cycle processor clock and can be used to drive other system components. all ac timings are referenced to clkout. the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series resistance): 60 ? max c0 (shunt capacitance of crystal): 7 pf max c l (load capacitance): 20 pf 2 pf drive level: 2 mw maximum
intel? 80c186ea core architecture 10 product name datasheet figure 2. clock configurations note: the l 1 c 1 network is only required when using a third-overtone crystal. 272432 3 (a) crystal connection 272432 4 (b) clock connection
intel? 80c186ea peripheral architecture product name datasheet 11 3.0 intel ? 80c186ea peripheral architecture the 80c186ea has integrated several common system peripherals with a cpu core to create a compact, yet powerful system. the integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or dma channels). the list of integrated peripherals include: 4-input interrupt control unit 3-channel timer/counter unit 2-channel dma unit 13-output chip-select unit refresh control unit power management logic the registers associated with each integrated peripheral are contained within a 128 x 16 register file called the peripheral control block (pcb). the pcb can be located in either memory or i/o space on any 256 byte address boundary. table 1 provides a list of the registers associated with the pcb when the processor's interrupt control unit is in master mode. in slave mode, the definitions of some registers change. table 2 provides register definitions specific to slave mode. 3.1 interrupt control unit the 80c186ea can receive interrupts from a number of sources, both internal and external. the interrupt control unit (icu) serves to merge these requests on a priority basis, for individual service by the cpu. each interrupt source can be independently masked by the interrupt control unit or all interrupts can be globally masked by the cpu. internal interrupt sources include the timers and dma channels. external interrupt sources come from the four input pins int3:0. the nmi interrupt pin is not controlled by the icu and is passed directly to the cpu. although the timers only have one request input to the icu, separate vector types are generated to service individual interrupts within the timer unit. 3.2 timer/counter unit the 80c186ea timer/counter unit (tcu) provides three 16-bit programmable timers. two of these are highly flexible and are connected to external pins for control or clocking. a third timer is not connected to any external pins and can only be clocked internally. however, it can be used to clock the other two timer channels. the tcu can be used to count external events, time external events, generate non-repetitive waveforms, generate timed interrupts, etc.
intel? 80c186ea peripheral architecture 12 product name datasheet table 1. peripheral control block registers pcb offset function pcb offset function pcb offset function pcb offset function 00h reserved 40h reserved 80h reserved c0h dma0 src. lo 02h reserved 42h reserved 82h reserved c2h dma0 src. hi 04h reserved 44h reserved 84h reserved c4h dma0 dest. lo 06h reserved 46h reserved 86h reserved c6h 08h reserved 48h reserved 88h reserved c8h dma0 count 0ah reserved 4ah reserved 8ah reserved cah dma0 control och reserved 4ch reserved 8ch reserved cch reserved 0eh reserved 4eh reserved 8eh reserved ceh reserved 10h reserved 50h timer 0 count 90h reserved d0h dma1 src. lo 12h reserved 52h timer 0 compare a 92h reserved d2h dma1 src. hi 14h reserved 54h timer 0 compare b 94h reserved d4h dma1 dest. lo 16h reserved 56h timer 0 control 96h reserved d6h dma1 dest. hi 18h reserved 58h timer 1 count 98h reserved d8h dma1 count 1ah reserved 5ah timer 1 compare a 9ah reserved dah dma1 control 1ch reserved 5ch timer 1 compare b 9ch reserved dch reserved 1eh reserved 5eh timer 1 control 9eh reserved deh reserved 20h reserved 60h timer 2 count a0h umcs e0h refresh base 22h end of interrupt 62h timer 2 compare a2h lmcs e2h refresh time 24h poll 64h reserved a4h pacs e4h refresh control 26h poll status 66h timer 2 control a6h mmcs e6h reserved 28h interrupt mask 68h reserved a8h mpcs e8h reserved 2ah priority mask 6ah reserved aah reserved eah reserved 2ch in-service 6ch reserved ach reserved ech reserved 2eh interrupt request 6eh reserved aeh reserved eeh reserved 30h interrupt status 70h reserved b0h reserved f0h power-save 32h timer control 72h reserved b2h reserved f2h power control 34h dma0 int. control 74h reserved b4h reserved f4h reserved 36h dma0 int. control 76h reserved b6h reserved f6h step id 38h int0 control 78h reserved b8h reserved f8h reserved 3ah int1 control 7ah reserved bah reserved fah reserved 3ch int2 control 7ch reserved bch reserved fch reserved 3eh int3 control 7eh reserved beh reserved feh relocation
intel? 80c186ea peripheral architecture product name datasheet 13 table 2. intel ? 80c186ea slave mode peripheral control block registers pcb offset function 20h interrupt vector 22h specific eoi 24h reserved 26h reserved 28h interrupt mask 2ah priority mask 2c in-service 2e interrupt request 30 interrupt status 32 tmr0 interrupt control 34 dma0 interrupt control 36 dma1 interrupt control 38 tmr1 interrupt control 3a tmr2 interrupt control 3c reserved 3e reserved
intel? 80c186ea peripheral architecture 14 product name datasheet 3.3 dma control unit the 80c186ea dma control unit provides two independent high-speed dma channels. data transfers can occur between memory and i/o space in any combination: memory to memory, memory to i/o, i/o to i/o or i/o to memory. data can be transferred either in bytes or words. transfers may proceed to or from either even or odd addresses, but even-aligned word transfers proceed at a faster rate. each data transfer consumes two bus cycles (a minimum of eight clocks), one cycle to fetch data and the other to store data. the chip-select/ready logic may be programmed to point to the memory or i/o space subject to dma transfers in order to provide hardware chip select lines. dma cycles run at higher priority than general processor execution cycles. 3.4 chip-select unit the 80c186ea chip-select unit integrates logic which provides up to 13 programmable chip- selects to access both memories and peripherals. in addition, each chip-select can be programmed to automatically terminate a bus cycle independent of the condition of the srdy and ardy input pins. the chip-select lines are available for all memory and i/o bus cycles, whether they are generated by the cpu, the dma unit, or the refresh control unit. 3.5 refresh control unit the refresh control unit (rcu) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. a 9-bit counter controls the number of clocks between refresh requests. a 9-bit address generator is maintained by the rcu with the address presented on the a9:1 address lines during the refresh bus cycle. address bits a19:13 are programmable to allow the refresh address block to be located on any 8 kbyte boundary. 3.6 power management the 80c186ea has three operational modes to control the power consumption of the device. they are power save mode, idle mode, and powerdown mode. power save mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency. an unmasked interrupt, nmi, or reset will cause the 80c186ea to exit power save mode. idle mode freezes the clocks of the execution unit and the bus interface unit at a logic zero state while all peripherals operate normally. powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. all internal registers hold their values provided vcc is maintained. current consumption is reduced to transistor leakage only.
intel? 80c186ea peripheral architecture product name datasheet 15 3.7 80c187 interface (80c186ea only) the 80c187 numerics coprocessor may be used to extend the 80c186ea instruction set to include floating point and advanced integer instructions. connecting the 80c186ea resout and test / busy pins to the 80c187 enables numerics mode operation. in numerics mode, three of the four mid- range chip select (mcs ) pins become handshaking pins for the interface. the exchange of data and control information proceeds through four dedicated i/o ports. if an 80c187 is not present, the 80c186ea configures itself for regular operation at reset. note: the 80c187 is not specified for 3v operation and therefore does not interface directly to the 80l186ea. 3.8 once test mode to facilitate testing and inspection of devices when fixed into a target system, the 80c186ea has a test mode available which forces all output and input/ output pins to be placed in the high- impedance state. once stands for ?on circuit emulation.? the once mode is selected by forcing the ucs and lcs pins low (0) during a processor reset (these pins are weakly held to a high (1) level) while resin is active.
intel? 80c186xl and intel? 80c186ea differences 16 product name datasheet 4.0 intel ? 80c186xl and intel ? 80c186ea differences the 80c186ea is intended as a direct functional upgrade for 80c186xl designs. in many cases, it will be possible to replace an existing 80c186xl with little or no hardware redesign. the following sections describe differences in pinout, operating modes, and ac and dc specifications to keep in mind. 4.1 pinout compatibility the 80c186ea requires a pdtmr pin to time the processor's exit from powerdown mode. the original pin arrangement for the 80c186xl in the plcc package did not have any spare leads to use for pdtmr. the arrangement of all the other leads in the 68-lead plcc is identical between the 80c186xl and the 80c186ea. therefore, upgrading a plcc 80c186xl to plcc 80c186ea is straightforward. 4.2 operating modes the 80c186xl has two operating modes, compatible and enhanced. compatible mode is a pin- to-pin replacement for the nmos 80186, except for numerics coprocessing. in enhanced mode, the processor has a refresh control unit, the power-save feature and an interface to the 80c187 numerics coprocessor. the mcs0 ,mcs1 ,andmcs3 pins change their functions to constitute handshaking pins for the 80c187. the 80c186ea allows all non-80c187 users to use all the mcs pins for chip-selects. in regular operation, all 80c186ea features (including those of the enhanced mode 80c186) are present except for the interface to the 80c187. numerics mode disables the three chip-select pins and reconfigures them for connection to the 80c187. 4.3 ttl vs. cmos inputs the inputs of the 80c186ea are rated for cmos switching levels for improved noise immunity, but the 80c186xl inputs are rated for ttl switching levels. in particular, the 80c186ea requires aminimumv ih of 3.5v to recognize a logic one while the 80c186xl requires a minimum v ih of only 1.9v (assuming 5.0v operation). the solution is to drive the 80c186ea with true cmos devices, such as those from the hc and ac logic families, or to use pull-up resistors where the added current draw is not a problem. 4.4 timing specifications 80c186ea timing relationships are expressed in a simplified format over the 80c186xl. the ac performance of an 80c186ea at a specified frequency will be very close to that of an 80c186xl at the same frequency. check the timings applicable to your design prior to replacing the 80c186xl.
intel? 80c186xl and intel? 80c186ea differences product name datasheet 17 4.5 package information this section describes the pins, pinouts, and thermal characteristics for the 80c186ea in the plastic leaded chip carrier (plcc) package. for complete package specifications and information, see the intel ? packaging outlines and dimensions guide (order number: 231369). with the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to -40 c to +85 c ambient. package types are identified by a two-letter prefix to the part number. the prefixes are listed in table 3 . 4.6 pin descriptions each pin or logical set of pins is described in table 5 . there are three columns for each entry in the pin description table. the pin name column contains a mnemonic that describes the pin function. negation of the signal name (for example, resin ) denotes a signal that is active low. the pin type column contains two kinds of information. the first symbol indicates whether a pin is power (p), ground (g), input only (i), output only (o) or input/output (i/o). some pins have multiplexed functions (for example, a19/s6). additional symbols indicate additional characteristics for each pin. table 5 lists all the possible symbols for this column. the input type column indicates the type of input (asynchronous or synchronous). asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge. synchronous pins require that setup and hold times be met to guarantee proper operation . for example, missing the setup or hold time for the srdy pin (a synchronous input) will result in a system failure or lockup. input pins may also be edge- or level-sensitive. the possible characteristics for input pins are s(e), s(l), a(e) and a(l). the output states column indicates the output state as a function of the device operating mode. output states are dependent upon the current activity of the processor. there are four operational states that are different from regular operation: bus hold, reset, idle mode and powerdown mode. appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in table 4 . the pin description column contains a text description of each pin. as an example, consider ad15:0. i/o signifies the pins are bidirectional. s(l) signifies that the input function is synchronous and level-sensitive. h(z) signifies that, as outputs, the pins are high- impedance upon acknowledgement of bus hold. r(z) signifies that the pins float during reset. p(x) signifies that the pins retain their states during powerdown mode. table3. prefixidentification prefix note package type temperature range tn plcc extended note: 1. the 25 mhz version is only available in commercial temperature range corresponding to 0 c to +70 c ambient.
intel? 80c186xl and intel? 80c186ea differences 18 product name datasheet table 4. pin description nomenclature symbol description p g i o i/o power pin (apply +v cc voltage) ground (connect to v ss ) input only pin output only pin input/output pin s(e) s(l) a(e) a(l) synchronous, edge sensitive synchronous, level sensitive asynchronous, edge sensitive asynchronous, level sensitive h(1) h(0) h(z) h(q) h(x) output driven to v cc during bus hold output driven to v ss during bus hold output floats during bus hold output remains active during bus hold output retains current state during bus hold r(wh) r(1) r(0) r(z) r(q) r(x) output weakly held at v cc during reset output driven to v cc during reset output driven to v ss during reset output floats during reset output remains active during reset output retains current state during reset i(1) i(0) i(z) i(q) i(x) output driven to v cc during idle mode output driven to v ss during idle mode output floats during idle mode output remains active during idle mode output retains current state during idle mode p(1) p(0) p(z) p(q) p(x) output driven to v cc during powerdown mode output driven to v ss during powerdown mode output floats during powerdown mode output remains active during powerdown mode output retains current state during powerdown mode
intel? 80c186xl and intel? 80c186ea differences product name datasheet 19 table 5. pin descriptions (sheet 1 of 3) pin name pin type input type output states description v cc p power connections consist of six pins which must be shorted externally to a v cc board plane. v ss g ground connections consist of five pins which must be shorted externally to a v ss board plane. clkin i a(e) clock input is an input for an external clock. an external oscillator operating at two times the required processor operating frequency can be connected to clkin. for crystal operation, clkin (along with oscout) are the crystal connections to an internal pierce oscillator. oscout o h(q) r(q) p(q) oscillator output is only used when using a crystal to generate the external clock. oscout (along with clkin) are the crystal r(q) connections to an internal pierce oscillator. this pin is not to be p(q) used as 2x clock output for non-crystal applications (i.e., this pin is n.c. for non-crystal applications). oscout does not float in once mode. clkout o h(q) r(q) p(q) clock output provides a timing reference for inputs and outputs of the processor, and is one-half the input clock (clkin) frequency. clkout has a 50% duty cycle and transitions every falling edge of clkin. resin ia(l) reset in causes the processor to immediately terminate any bus cycle in progress and assume an initialized state. all pins will be driven to a known state, and resout will also be driven active. the rising edge (low-to-high) transition synchronizes clkout with clkin before the processor begins fetching opcodes at memory location 0ffff0h. resout o h(0) r(i) p(o) reset output that indicates the processor is currently in the reset state. resout will remain active as long as resin remains active. when tied to the test /busy pin, resout forces the 80c186ea into numerics mode. pdtmr i/o a(l) h(wh) r(z) p(1) power-down timer pin (normally connected to an external capacitor) that determines the amount of time the processor waits after an exit from power down before resuming normal operation. p(1) the duration of time required will depend on the startup characteristics of the crystal oscillator. nmi i a(e) non-maskable interrupt input causes a type 2 interrupt to be serviced by the cpu. nmi is latched internally. test /busy (test ) ia(e) test /busy is sampled upon reset to determine whether the 80c186ea is to enter numerics mode. in regular operation, the pin is test . test is used during the execution of the wait instruction to suspend cpu operation until the pin is sampled active (low). in numerics mode, the pin is busy. busy notifies the 80c186ea of 80c187 numerics coprocessor activity. ad15:0 (ad7:0) i/o s(l) h(z) r(z) p(x) these pins provide a multiplexed address and data bus. during the address phase of the bus cycle, address bits 0 through 15 (0 through 7 on the 8-bit bus versions) are presented on the bus and can be latched using ale. 8- or 16-bit data information is transferred during the data phase of the bus cycle. a18:16 a19/s6?a16 (a19?a8) oh(z) r(z) p(x) these pins provide multiplexed address during the address phase of the bus cycle. address bits 16 through 19 are presented on these pins and can be latched using ale. a18:16 are driven to a logic 0 during the data phase of the bus cycle. on the 8-bit bus versions, a15?a8 provide valid address information for the entire bus cycle. also during the data phase, s6 is driven to a logic 0 to indicate a cpu-initiated bus cycle or logic 1 to indicate a dma-initiated bus cycle or a refresh cycle.
intel? 80c186xl and intel? 80c186ea differences 20 product name datasheet s2:0 oh(z) r(z) p(1) bus cycle status are encoded on these pins to provide bus transaction information. s2:0 are encoded as follows: s2 s1 s0 bus cycle initiated 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 interrupt acknowledge read i/o write i/o processor halt queue instruction fetch read memory write memory passive (no bus activity) ale/qs0 o h(0) r(0) p(0) address latch enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle. in queue status mode, qs0 provides queue status information along with qs1. bhe (rfsh ) oh(z) r(z) p(x) byte high enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus. bhe anda0have the following logical encoding: a0 bhe encoding (for 80c186ea/80l186ea only) 0 0 1 1 0 1 0 1 word transfer even byte transfer oddbytetransfer refresh operation on the 80c188ea/80l188ea, rfsh is asserted low to indicate a refresh bus cycle. rd /qsmd oh(z) r(wh) p(1) read output signals that the accessed memory or i/o device must drive data information onto the data bus. upon reset, this pin has an alternate function. as qsmd , it enables queuestatusmode when grounded. in queue status mode, the ale/qs0 and wr /qs1 pins provide the following information about processor/instruction queue interaction: qs1 qs0 queue operation 0 0 1 1 0 1 1 0 no queue operation first opcode byte fetched from the queue subsequent byte fetched from the queue empty the queue wr /qs1 o h(z) r(z) p(1) write output signals that data available on the data bus are to be written into the accessed memory or i/o device. in queue status mode, qs1 provides queue status information along with qs0. ardy i a(l) s(l) asynchronous ready is an input to signal for the end of a bus cycle. ardy is asynchronous on rising clkout and synchronous on falling clkout. ardy or srdy must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the chip select unit. srdy i s(l) synchronous ready is an input to signal for the end of a bus cycle. ardy or srdy must be active to terminate any processor bus cycle, unless they are ignored due to correct programming of the chip select unit. den oh(z) r(z) p(1) data enable output to control the enable of bidirectional transceivers when buffering a system. den is active only when data is to be transferred on the bus. lock oh(z) r(wh) p(1) lock output indicates that the bus cycle in progress is not to be interrupted. the processor will not service other bus requests (such as hold) while lock is active. this pin is configured as a weakly held high input while resin is active and must not be driven low. table 5. pin descriptions (sheet 2 of 3) pin name pin type input ty pe output states description
intel? 80c186xl and intel? 80c186ea differences product name datasheet 21 hold i a(l) hold request input to signal that an external bus master wishes to gain control of the local bus. the processor will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. hlda o h(1) r(0) p(0) hold acknowledge output to indicate that the processor has relinquished control of the local bus. when hlda is asserted, the processor will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly. ucs oh(1) r(1) p(1) upper chip select will go active whenever the address of a memory or i/o bus cycle is within the address limitations programmed by the user. after reset, ucs is configured to be active for memory accesses between 0ffc00h and 0fffffh. during a processor reset, ucs and lcs are used to enable once mode. lcs oh(1) r(1) p(1) lower chip select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user. r(1) lcs is inactive after a reset. during a processor reset, ucs and lcs are used to enable once mode. mcs0 /pereq mcs1 /error mcs2 mcs3 /ncs i/o a(l) h(1) r(1) p(1) these pins provide a multiplexed function. if enabled, these pins normally comprise a block of mid-range chip select outputs which will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user. in numerics mode (80c186ea only), three of the pins become handshaking pins for the 80c187. the coprocessor request input signals that a data transfer is pending. error is an input which indicates that the previous numerics coprocessor operation resulted in an exception condition. an interrupt type 16 is generated when error is sampled active at the beginning of a numerics operation. numerics coprocessor select is an output signal generated when the processor accesses the 80c187. pcs4:0 oh(1) r(1) p(1) peripheral chip selects go active whenever the address of a memory or i/o bus cycle is within the address limitations programmed by the user. pcs5 /a1 pcs6 /a2 oh(1)/ h(x) r(1) p(1) these pins provide a multiplexed function. as additional peripheral chip selects , they go active whenever the address of a memory or i/o bus cycle is within the address limitations by the user. they may also be programmed to provide latched address a2:1 signals. t0out t1out oh(q) r(1) p(q) timer output pinscanbeprogrammedtoprovideasingleclockor continuous waveform generation, depending on the timer mode selected. t0in i a(l) a(e) timer input is used either as clock or control signals, depending on the timer mode selected. t1in a(e) drq0 drq1 ia(l) dma request is asserted by an external request when it is prepared for a dma transfer. int0 int1/select ia(e,l) maskable interrupt input will cause a vector to a specific type interrupt routine. to allow interrupt expansion, int0 and/or int1 can be used with inta0 and inta1 to interface with an external slave controller. int1 becomes select when the icu is configured for slave mode. int2/inta0 int3/inta1 /irq i/o a(e,l) h(1) r(z) p(1) these pins provide multiplexed functions. as inputs, they provide a maskable interrupt that will cause the cpu to vector to a specific type interrupt routine. as outputs, each is programmatically controlled to provide an interrupt acknowledge handshake signal to allow interrupt expansion. int3/inta1 becomes irq when the icu is configured for slave mode. n.c. no connect. for compatibility with future products, do not connect to these pins. note: pin names in parentheses apply to the 80c188ea and 80l188ea. table 5. pin descriptions (sheet 3 of 3) pin name pin type input type output states description
intel? 80c186ea pinout 22 product name datasheet 5.0 intel ? 80c186ea pinout table 6 and table 7 list the 80c186ea pin names with package location for the 68-pin plastic leaded chip carrier (plcc) component. figure 3 depicts the complete 80c186ea/80l186ea pinout (plcc package) as viewed from the top side of the component (i.e., contacts facing down). table 6. plcc pin names with package location address/data bus bus control processor control i/o name location name location name location name location ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 (a8) ad9 (a9) ad10 (a10) ad11 (a11) ad12 (a12) ad13 (a13) ad14 (a14) ad15 (a15) a16 a17 a18 a19/s6 17 15 13 11 8 6 4 2 16 14 12 10 7 5 3 1 68 67 66 65 ale/qs0 bhe (rfsh ) s0 s1 s2 rd /qsmd wr /qs1 ardy srdy den lock hold hlda 61 64 52 53 54 62 63 55 49 39 48 50 51 resin resout clkin oscout clkout test /busy pdtmr nmi int0 int1/select int2/inta0 int3/inta1 / irq 24 57 59 58 56 47 40 46 45 44 42 41 ucs lcs mcs0 /pereq mcs1 /error mcs2 mcs3 /ncs pcs0 pcs1 pcs2 pcs3 pcs4 pcs5 /a1 pcs6 /a2 t0out t0in t1out t1in drq0 drq1 34 33 38 37 36 35 25 27 28 29 30 31 32 22 20 23 21 18 19 power name location v ss v cc 26, 60 9, 43 note: pin names in parentheses apply to the 80c188ea/80l188ea. table 7. plcc package location with pin names location name location name location name location name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ad15 (a15) ad7 ad14 (a14) ad6 ad13 (a13) ad5 ad12 (a12) ad4 v cc ad11 (a11) ad3 ad10 (a10) ad2 ad9 (a9) ad1 ad8 (a8) ad0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 drq0 drq1 t0in t1in t0out t1out resin pcs0 v ss pcs1 pcs2 pcs3 pcs4 pcs5 /a1 pcs6 /a2 lcs ucs 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 mcs3 /ncs mcs2 mcs1 /error mcs0 /pereq den pdtmr int3/inta1 / irq int2/inta0 vcc int1/select int0 nmi test /busy lock srdy hold hlda 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 s0 s1 s2 ardy clkout resout oscout clkin v ss ale/qs0 rd /qsmd wr /qs1 bhe rfsh a19/s6 a18 a17 a16 note: pin names in parentheses apply to the 80c188ea/80l188ea.
intel? 80c186ea pinout product name datasheet 23 figure 3. 68-lead plcc pinout diagram notes: 1. the nine character alphanumeric code (xxxxxxxxd) underneath the product number is the intel fpo number. 2. pin names in parentheses apply to the 80c186ea/80l188ea.
package thermal specifications 24 product name datasheet 6.0 package thermal specifications the 80c186ea/80l186ea is specified for operation when t c (the case temperature) is within the range of 0c to 85c (plcc package). t c may be measured in any environment to determine whether the processor is within the specified operating range. the case temperature must be measured at the center of the top surface. t a (the ambient temperature) can be calculated from ca (thermal resistance from the case to ambient) with the following equation: t a =t c -p ca typical values for ca at various airflows are given in table 8 . p (the maximum power consumption, specified in watts) is calculated by using the maximum icc as tabulated in the dc specifications and v cc of 5.5 v. table 8. thermal resistance ( ca ) at various airflows (in c/watt) airflow linear ft./min. (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) ca (plcc) 29 25 21 19 17 16.5
electrical specification product name datasheet 25 7.0 electrical specification 7.1 absolute maximum ratings* note: this data sheet contains preliminary information on new products in production. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 7.2 recommended connections power and ground connections must be made to multiple v cc and v ss pins. every 80c186ea based circuit board should contain separate power (v cc ) and ground (v ss )planes.allv cc and v ss pins must be connected to the appropriate plane. pins identified as ?n.c.? must not be connected in the system. decoupling capacitors should be placed near the processor. the value and type of decoupling capacitors is application and board layout dependent. the processor can cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads. always connect any unused input pins to an appropriate signal level. in particular, unused interrupt pins (nmi, int3:0) should be connected to v ss to avoid unwanted interrupts. leave any unused output pin or any ?n.c.? pin unconnected. storage temperature: -65 c to + 150 c case temperature under bias: -65 c to + 150 c supply voltage with respect to v ss :-0.5vto+6.5v voltage on other pins with respect to v ss :-0.5vtov cc +0.5v
dc specifications 26 product name datasheet 8.0 dc specifications table 9. dc specifications (80c186ea/80c 188ea) notes: 1.rd /qsmd , ucs ,lcs ,mcs0 /pereq, mcs1 /error ,lock and test /busy have internal pull-ups that are only activated during reset. loading these pins above i ol = -275 a will cause the processor to enter alternate modes of operation. 2.output pins are floated using hold or once mode. 3.measured at worst case temperature and v cc with all outputs loaded as specified in the ac test conditions, and with the device in reset (resin held low). reset is worst case for i cc . 4.output capacitance is the capacitive load of a floating output pin. 5.operating conditions for 25 mhz are 0 cto+70 c, v cc = 5.0v 10%. () symbol parameter min max units conditions v cc supply voltage 45 55 v v il input low voltage for all pins b 05 03 v cc v v ih input high voltage for all pins 07 v cc v cc a 05 v v ol output low voltage 045 v i ol e 3ma(min) v oh output high voltage v cc b 05 v i oh eb 2ma(min) v hyr input hysterisis on resin 030 v i il1 input leakage current (except g 10 m a0v s v in s v cc rd qsmd ucs lcs mcs0 pereq mcs1 error lock and test busy) i il2 input leakage current b 275 m av in e 07 v cc (rd qsmd ucs lcs mcs0 pereq (note 1) mcs1 error lock and test busy i ol output leakage current g 10 m a 045 s v out s v cc (note 2) i cc supply current cold (reset) 80c186ea2580c188ea25 105 ma (notes 3 5) 80c186ea2080c188ea20 90 ma 80c186ea1380c188ea13 65 ma i id supply current in idle mode 80c186ea2580c188ea25 90 ma (note 5) 80c186ea2080c188ea20 70 ma 80c186ea1380c188ea13 46 ma i pd supply current in powerdown mode 80c186ea2580c188ea25 100 m a (note 5) 80c186ea2080c188ea20 100 m a 80c186ea1380c188ea13 100 m a c out output pin capacitance 0 15 pf t f e 1 mhz (note 4) c in input pin capacitance 0 15 pf t f e 1 mhz
dc specifications product name datasheet 27 table 10. dc specifications (80l186ea/80l188ea) notes: 1.rd /qsmd , ucs ,lcs ,mcs0 ,mcs1 ,lock and test have internal pull-ups that are only activated during reset. loading these pins above i ol = -275 a will cause the processor to enter alternate modes of operation. 2.output pins are floated using hold or once mode. 3.measured at worst case temperature and v cc with all outputs loaded as specified in the ac test conditions, and with the device in reset (resin held low). 4.output capacitance is the capacitive load of a floating output pin.
dc specifications 28 product name datasheet 8.1 i cc versus frequency and voltage the current (i cc ) consumption of the processor is essentially composed of two components; ipd and iccs. i pd is the quiescent current that represents internal device leakage, and is measured with all inputs or floating outputs at gnd or v cc (no clock applied to the device). i pd is equal to the powerdown current and is typically less than 50 a. i ccs is the switching current used to charge and discharge parasitic device capacitance when changing logic levels. since i ccs is typically much greater than i pd ,i pd can often be ignored when calculating i cc . i ccs is related to the voltage and frequency at which the device is operating. it is given by the formula: measuring c dev on a device like the 80c186ea would be difficult. instead, c dev is calculated using the above formula by measuring i cc at a known v cc and frequency (see table 11 ). using this c dev value, i cc can be calculated at any voltage and frequency within the specified operating range. example: calculate the typical i cc when operating at 20 mhz, 4.8v. i cc =i ccs =4.80.51520 49 ma power=vi=v 2 c dev f i=i cc =i ccs =vc dev f where: v = device operating voltage (v cc ) c dev = device capacitance f = device operating frequency i ccs =i cc = device current table 11. c dev values parameter type max units notes c dev (device in reset) 0.515 0.905 ma/v*mhz 1,2 c dev (device in idle) 0.391 0.635 ma/v*mhz 1,2 1. max c dev is calculated at -40 c, all floating outputs driven to v cc orgnd,andalloutputsloadedto50pf (including clkout and oscout). 2. typical c dev is calculated at 25 c with all outputs loaded to 50 pf except clkout and oscout, which are not loaded.
dc specifications product name datasheet 29 8.2 pdtmr pin delay calculation the pdtmr pin provides a delay between the assertion of nmi and the enabling of the internal clocks when exiting powerdown. a delay is required only when using the on-chip oscillator to allow the crystal or resonator circuit time to stabilize. note: the pdtmr pin function does not apply when resin is asserted (i.e., a device reset during powerdown is similar to a cold reset and resin must remain active until after the oscillator has stabilized). to calculate the value of capacitor required to provide a desired delay, use the equation: example 1. to get a delay of 300 s, a capacitor value of c pd =440 (300 10 -6 )=0.132fis required. round up to standard (available) capacitive values. note: the above equation applies to delay times greater than 10 s and will compute the typical capacitance needed to achieve the desired delay. a delay variance of +50% or -25% can occur due to temperature, voltage, and device process extremes. in general, higher v cc and/or lower temperature will decrease delay time, while lower v cc and/or higher temperature will increase delay time. 440t=c pd (5v, 25 c) where: t = desired delay in seconds c pd = capacitive load on pdtmr in microfarads
ac specifications 30 product name datasheet 9.0 ac specifications table 12. ac characteristics ? 80c186ea25/80c186ea20/80c186ea13 (sheet 1 of 2) symbol parameter minmax minmax minmax units notes input clock 25 mhz (12) 20 mhz 13 mhz t f clkin frequency 0 50 0 40 0 26 mhz 1 t c clkin period 20 % 25 % 385 % ns 1 t ch clkin high time 10 % 10 % 12 % ns 1 2 t cl clkin low time 10 % 10 % 12 % ns 1 2 t cr clkin rise time 1 8 1 8 1 8 ns 1 3 t cf clkin fall time 1 8 1 8 1 8 ns 1 3 output clock t cd clkin to clkout delay 0 15 0 17 0 23 ns 1 4 t clkout period 2t c 2 t c 2 t c ns 1 t ph clkout high time (t2) b 5 (t2) b 5 (t2) b 5ns1 t pl clkout low time (t2) b 5 (t2) b 5 (t2) b 5ns1 t pr clkout rise time 1 6 1 6 1 6 ns 1 5 t pf clkout fall time 1 6 1 6 1 6 ns 1 5 output delays t chov1 ale s20 den 3 20 3 22 3 25 ns 1 4 6 7 bhe (rfsh ) lock a1916 t chov2 mcs30 lcs ucs pcs60 3 25 3 27 3 30 ns 1 4 6 8 ncs rd wr t clov1 bhe (rfsh ) den lock 3 20 3 22 3 25 ns 1 4 6 resout hlda t0out t1out a1916 t clov2 rd wr mcs30 lcs 3 25 3 27 3 30 ns 1 4 6 ucs pcs60 ad150 (a158 ad70) ncs inta10 s20 t chof rd wr bhe (rfsh ) 0 25 0 25 0 25 ns 1 lock s20 a1916 t clof den ad150 (a158 ad70) 0 25 0 25 0 25 ns 1
ac specifications product name datasheet 31 notes: 1.see ac timing waveforms , for waveforms and definition. 2.measured at v ih for high time, v il for low time. 3.only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4.specifiedfora50pfload,see figure 9 for capacitive derating information. 5.specifiedfora50pfload,see figure 10 for rise and fall times outside 50 pf. 6.see figure 10 for rise and fall times. 7.t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8.t chov2 applies to rd and wr only after a hold release. 9.setup and hold are required to guarantee recognition. 10.setup and hold are required for proper operation. 11.t chovs applies to bhe (rfsh ) and a19:16 only after a hold release. 12.operating conditions for 25 mhz are 0 cto+70 c, v cc =5.0v10%. 13.pin names in parentheses apply to the 80c188ea/80l188ea. table 12. ac characteristics ? 80c186ea25/80c186ea20/80c186ea13 (sheet 2 of 2) symbol parameter minmax minmax minmax units notes synchronous inputs 25 mhz (12) 20 mhz 13 mhz t chis test nmi int30 8 10 10 ns 1 9 t10in ardy t chih test nmi int30 3 3 3 ns 1 9 t10in ardy t clis ad150 (ad70) ardy 10 10 10 ns 1 10 srdy drq10 t clih ad150 (ad70) ardy 3 3 3 ns 1 10 srdy drq10 t clis hold pereq error 10 10 10 ns 1 9 (80c186ea only) t clih hold pereq error 3 3 3 ns 1 9 (80c186ea only) t clis resin (to clkin) 10 10 10 ns 1 9 t clih resin (fromclkin) 3 3 3 ns 1 9
ac specifications 32 product name datasheet table 13. ac characteristics ? 80l186ea13/80c186ea8 symbol parameter min. max. units notes input clock t f clkin frequency 0 26 mhz 1 t c clkin period 38.5 ns 1 t ch clkin high time 12 ns 1,2 t cl clkin low time 12 ns 1,2 t cr clkin rise time 1 8 ns 1,3 t cf clkin fall time 1 8 ns 1,3 output clock t cd clkin to clkout delay 0 45 ns 1,4 tclkoutperiod 2*t c ns 1 t ph clkout high time (t/2) ? 5ns1 t pl clkout low time (t/2) ? 5ns1 t pr clkout rise time 1 12 ns 1,5 t pf clkout fall time 1 12 ns 1,5 output delays t chov1 ale, lock 3 27 ns 1,4,6,7 t chov2 mcs3:0 ,lcs , ucs ,pcs6:0 ,rd ,wr 3 32 ns 1,4,6,8 t chov3 s2:0 ,(den ), bhe ,(rfsh ), a19:16 3 30 ns 1 t clov1 lock , resout, hlda, t0out, t1out 3 27 ns 1, 4, 6 t clov2 rd ,wr ,mcs3:0 ,lcs , ucs ,pcs6:0 ,inta1:0 3 32 ns 1,4,6 t clov3 bhe ,(rfsh ), den , a19:16 3 30 ns 1, 4, 6 t clov4 ad15:0, (a15:8, ad7:0) 3 3 ns 1, 4, 6 t clov5 s2:0 3 38 ns 1,4,6 t chof rd ,wr ,bhe ,(rfsh ), lock ,s2:0 , a19:16 0 27 ns 1 t clof den , ad15:0, (a15:8, ad7:0) 0 27 ns 1 synchronous inputs t chis test ,nmi,int3:0,t1:0in,ardy 22 ns 1,9 t chih test ,nmi,int3:0,t1:0in,ardy 3 ns 1,9 t clis ad15:0, (ad7:0), ardy, srdy, drq1:0 22 ns 1, 10 t clih ad15:0, (ad7:0), ardy, srdy, drq1:0 3 ns 1, 10 t clis hold 22 ns 1, 9 t clih hold 3 ns 1, 9 t clis resin (to clkin) 22 ns 1, 9 t clih resin (from clkin) 3 ns 1, 9 notes: 1. see ac timing waveforms , for waveforms and definition. 2. measured at v ih for high time, v il for low time. 3. only required to guarantee i cc . maximum limits are bounded by t c ,t ch and t cl . 4. specified for a 50 pf load, see figure 9 for capacitive derating information. 5. specified for a 50 pf load, see figure 10 for rise and fall times outside 50 pf. 6. see figure 10 for rise and fall times. 7. t chov1 applies to bhe (rfsh ), lock and a19:16 only after a hold release. 8. t chov2 applies to rd and wr only after a hold release. 9. setup and hold are required to guarantee recognition. 10.setup and hold are required for proper operation. 11. t chovs applies to bhe (rfsh ) and a19:16 only after a hold release. 12.pin names in parentheses apply to the 80c188ea/80l188ea.
ac specifications product name datasheet 33 table 14. relative timings (80c186ea25/20/13, 80l186ea13) notes: 1. assumes equal loading on both pins. 2.canbeextendedusingwaitstates. 3. not tested. 4. not applicable to latched a2:1. these signals change only on falling t 1 . 5.forwritecyclefollowedbyreadcycle. 6. operating conditions for 25 mhz are 0 cto+70 c, v cc =5.0v10%. symbol parameter minmax unit notes relative timings t lhll ale rising to ale falling t b 15 ns t avll address valid to ale falling t b 10 ns t plll chip selects valid to ale falling t b 10 ns 1 t llax address hold fromale falling t b 10 ns t llwl ale falling to wr falling t b 15 ns 1 t llrl ale falling to rd falling t b 15 ns 1 t rhlh rd rising to ale rising t b 10 ns 1 t whlh wr rising to ale rising t b 10 ns 1 t afrl address float to rd falling 0 ns t rlrh rd falling to rd rising (2 t) b 5ns2 t wlwh wr falling to wr rising (2 t) b 5ns2 t rhav rd rising to address active t b 15 ns t whdx output data hold after wr rising t b 15 ns t whdex wr rising to den rising t b 10 ns 1 t whph wr rising to chip select rising t b 10 ns 1 4 t rhph rd rising to chip select rising t b 10 ns 1 4 t phpl cs inactive to cs active t b 10 ns 1 t ovrh once (ucs lcs ) active to resin rising t ns 3 t rhox once (ucs lcs ) to resin rising t ns 3
ac test conditions 34 product name datasheet 10.0 ac test conditions the ac specifications are tested with the 50 pf load shown in figure 4 . see the derating curves section to see how timings vary with load capacitance. specifications are measured at the v cc /2 crossing point, unless otherwise specified. see ac timing waveforms, for ac specification definitions, test pins, and illustrations. figure 4. ac test load note: c l = 50 pf for all signals.
ac timing waveforms product name datasheet 35 11.0 ac timing waveforms figure 5. input and output clock waveform figure 6. output delay and float waveform note: 20% v cc k float k 80% v cc
ac timing waveforms 36 product name datasheet figure 7. input setup and hold note: resin measured to clkin, not clkout
ac timing waveforms product name datasheet 37 figure 8. relative signal waveform notes: pin names in parentheses apply to the 80c188ea t lhll t avll t llax t whlh v cc ale rd# or wr# add:15 [ad0:7] a19:16 [a19:8] mcs3:0#, lcs#, ucs#, pcs6:0# clkout ov v cc ov den# v cc ov resin# ov ucs#, lcs# v cc ov v cc ov 50% 50% 50% 50% 50% 50% 50% t rhlh t whdx t afrl t rlrh t wlwh t llrl t llwl 50% t phpl t plll t rhph t whph t rhav t whdex 50% 50% 50% t ovrh t rhox 50% 50% 50% 50% 50%
derating curves 38 product name datasheet 12.0 derating curves figure 9. typical output delay variations versus load capacitance figure 10. typical rise and fall variations versus load capacitance
reset product name datasheet 39 13.0 reset the processor performs a reset operation any time the resin pin is active. the resin pin is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. from a power-on state, resin must be held active (low) in order to guarantee correct initialization of the processor. failure to provide resin while the device is powering up will result in unspecified operation of the device. figure 11 shows the correct reset sequence when first applying power to the processor. an external clock connected to clkin must not exceed the v cc threshold being applied to the processor. this is normally not a problem if the clock driver is supplied with the same v cc that supplies the processor. when attaching a crystal to the device, resin must remain active until both v cc and clkout are stable (the length of time is application specific and depends on the startup characteristics of the crystal circuit). the resin pin is designed to operate correctly using an rc reset circuit, but the designer must ensure that the ramp time for v cc is not so long that resin is never really sampled at a logic low level when v cc reaches minimum operating conditions. figure 12 shows the timing sequence when resin is applied after v cc is stable and the device has been operating. note that a reset will terminate all activity and return the processor to a known operating state. any bus operation that is in progress at the time resin is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating). while resin is active, signals rd /qsmd ,ucs ,lcs ,mcs0 /pereq, mcs1 /error ,lock , and test /busy are configured as inputs and weakly held high by internal pull-up transistors. forcing ucs and lcs low selects once mode. forcing qsmd low selects queue status mode. forcing test / busy high at reset and low four clocks later enables numerics mode. forcing lock low is prohibited and results in unspecified operation.
reset 40 product name datasheet figure 11. powerup reset waveforms notes: 1. clkout synchronization occurs approximately 1 ? clkin periods after resin# is sampled low. 2. pin names in parentheses apply to the 80c188ea.
reset product name datasheet 41 figure 12. warm reset waveforms notes: 1. clkout resynchronization occurs approximately 1 ? clkin periods after resin# is sampled low. if resin# is sampled low while transitioning high, then clkout will remain high for two clkin periods. if resin# is sampled low while clkout is transitioning high, the clkout will not be affected. 2. pin names in parentheses apply to the 80c188ea.
bus cycle waveforms 42 product name datasheet 14.0 bus cycle waveforms figure 13 through figure 19 present the various bus cycles that are generated by the processor. what is shown in the figure is the relationship of the various bus signals to clkout. these figures along with the information present in ac specifications allow the user to determine all the critical timing analysis needed for a given application. figure 13. read, fetch and refresh cycle waveform notes: 1. during the data phase of the bus cycle, a19/s6 is driven high for a dma or refresh cycle. 2. pin names in parentheses apply to the 80c188ea.
bus cycle waveforms product name datasheet 43 figure 14. write cycle waveform notes: 1. during the data phase of the bus cycle, a19/s6 is driven high for a dma cycle. 2. pin names in parentheses apply to the 80c188ea.
bus cycle waveforms 44 product name datasheet figure 15. halt cycle waveform notes: 1. the processor drives these pins to 0 during idle and powerdown modes. 2. pin names in parentheses apply to the 80c188ea.
bus cycle waveforms product name datasheet 45 figure 16. inta cycle waveform notes: 1. inta# occurs one clock later in slave mode. 2. pin names in parentheses apply to the 80c188ea.
bus cycle waveforms 46 product name datasheet figure 17. hold/hlda waveform note: pin names in parentheses apply to the 80c188ea.
bus cycle waveforms product name datasheet 47 figure 18. dram refresh cycle during hold acknowledge note: pin names in parentheses apply to the 80c188ea.
bus cycle waveforms 48 product name datasheet figure 19. ready waveform notes: 1. generalized diagram for read or write. 2. ardy low by either edge causes a wait state. only rising ardy is fully synchronized. 3. srdy low causes a wait state. srdy must meet setup and hold times to ensure correct device operation. 4. either ardy or srdy active high will terminate a bus cycle. 5. pin names in parentheses apply to the 80c188ea.
product name execution timings product name datasheet 49 15.0 product name execution timings a determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions. the following instruction timings represent the minimum execution time in clock cycle for each instruction. the timings given are based on the following assumptions: the opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. no wait states or bus holds occur. all word-data is located on even-address boundaries. (80c186ea only) all jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. all instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (biu) and execution unit. with a 16-bit biu, the 80c186ea has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. therefore, actual program execution time will not be substantially greater than that derived from adding the instruction timings shown. the 80c188ea 8-bit biu is limited in its performance relative to the execution unit. a sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown.
product name execution timings 50 product name datasheet figure 20. instruction set summary function format 80c186ea 80c188ea comments clock clock cycles cycles data transfer mov e move register to registermemory 1000100w modreg rm 212 212 registermemory to register 1000101w modreg rm 29 29 immediatetoregistermemory 1100011w mod000 rm data dataifw e 1 12C13 12C13 816-bit immediatetoregister 1011w reg data dataifw e 1 3C4 3C4 816-bit memory to accumulator 1010000w addr-low addr-high 8 8 accumulator to memory 1010001w addr-low addr-high 9 9 registermemory to segment register 10001110 mod0reg rm 29 213 segment register to registermemory 10001100 mod0reg rm 211 215 push e push memory 11111111 mod110 rm 16 20 register 01010 reg 10 14 segment register 000reg110 9 13 immediate 011010s0 data dataifs e 01014 pusha e push all 01100000 36 68 pop e pop memory 10001111 mod000 rm 20 24 register 01011 reg 10 14 segment register 000reg111 (reg i 01) 8 12 popa e popall 01100001 51 83 xchg e exchange registermemory with register 1000011w modreg rm 417 417 register with accumulator 10010 reg 3 3 in e input from fixedport 1110010w port 10 10 variableport 1110110w 8 7 out e output to fixedport 1110011w port 9 9 variableport 1110111w 7 7 xlat e translate byte to al 11010111 11 15 lea e load ea to register 10001101 modreg rm 6 6 lds e load pointer to ds 11000101 modreg rm (mod i 11) 18 26 les e load pointer to es 11000100 modreg rm (mod i 11) 18 26 lahf e load ah with flags 10011111 2 2 sahf e storeahintoflags 10011110 3 3 pushf e push flags 10011100 9 13 popf e popflags 10011101 8 12 shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
product name execution timings product name datasheet 51 figure 20. instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles data transfer (continued) segment e segment override cs 00101110 2 2 ss 00110110 2 2 ds 00111110 2 2 es 00100110 2 2 arithmetic add e add regmemory with register to either 000000dw modreg rm 310 310 immediatetoregistermemory 100000sw mod000 rm data dataifsw e 01 416 416 immediate to accumulator 0000010w data dataifw e 1 34 34 816-bit adc e add with carry regmemory with register to either 000100dw modreg rm 310 310 immediatetoregistermemory 100000sw mod010 rm data dataifsw e 01 416 416 immediate to accumulator 0001010w data dataifw e 1 34 34 816-bit inc e increment registermemory 1111111w mod000 rm 315 315 register 01000 reg 3 3 sub e subtract regmemory and register to either 001010dw modreg rm 310 310 immediatefrom registermemory 100000sw mod101 rm data dataifsw e 01 416 416 immediate from accumulator 0010110w data dataifw e 1 34 34 816-bit sbb e subtract with borrow regmemory and register to either 000110dw modreg rm 310 310 immediatefrom registermemory 100000sw mod011 rm data dataifsw e 01 416 416 immediate from accumulator 0001110w data dataifw e 1 34 34 816-bit dec e decrement registermemory 1111111w mod001 rm 315 315 register 01001 reg 3 3 cmp e compare registermemory with register 0011101w modreg rm 310 310 register with registermemory 0011100w modreg rm 310 310 immediatewithregistermemory 100000sw mod111 rm data dataifsw e 01 310 310 immediate with accumulator 0011110w data dataifw e 1 34 34 816-bit neg e change sign registermemory 1111011w mod011 rm 310 310 aaa e ascii adjust for add 00110111 8 8 daa e decimal adjust for add 00100111 4 4 aas e ascii adjust for subtract 00111111 7 7 das e decimal adjust for subtract 00101111 4 4 mul e multiply (unsigned) 1111011w mod100 rm register-byte 26C28 26C28 register-word 35C37 35C37 memory-byte 32C34 32C34 memory-word 41C43 41C48 shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
product name execution timings 52 product name datasheet figure 20. instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles arithmetic (continued) imul e integer multiply (signed) 1111011w mod101 rm register-byte 25C28 25C28 register-word 34C37 34C37 memory-byte 31C34 32C34 memory-word 40C43 40C43 imul e integer immediate multiply 011010s1 modreg rm data data if s e 0 22C25 22-25 (signed) 29C32 29C32 div e divide (unsigned) 1111011w mod110 rm register-byte 29 29 register-word 38 38 memory-byte 35 35 memory-word 44 44 idiv e integer divide (signed) 1111011w mod111 rm register-byte 44C52 44C52 register-word 53C61 53C61 memory-byte 50C58 50C58 memory-word 59C67 59C67 aam e ascii adjust for multiply 11010100 00001010 19 19 aad e ascii adjust for divide 11010101 00001010 15 15 cbw e convert byte to word 10011000 2 2 cwd e convert word to double word 10011001 4 4 logic shiftrotate instructions registermemory by 1 1101000w modtttrm 215 215 registermemory by cl 1101001w modtttrm 5 a n17 a n5 a n17 a n registermemory by count 1100000w modtttrm count 5 a n17 a n5 a n17 a n ttt instruction 000 rol 001 ror 010 rcl 011 rcr 1 0 0 shlsal 101 shr 111 sar and e and regmemory and register to either 001000dw modreg rm 310 310 immediate to registermemory 1000000w mod100 rm data data if w e 1 416 416 immediate to accumulator 0010010w data data if w e 1 34 34 816-bit test e and function to flags no result registermemory and register 1000010w modreg rm 310 310 immediate data and registermemory 1111011w mod000 rm data data if w e 1 410 410 immediate data and accumulator 1010100w data data if w e 1 34 34 816-bit or e or regmemory and register to either 000010dw modreg rm 310 310 immediate to registermemory 1000000w mod001 rm data data if w e 1 416 416 immediate to accumulator 0000110w data data if w e 1 34 34 816-bit shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
product name execution timings product name datasheet 53 figure 20. instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles logic (continued) xor e exclusive or regmemory and register to either 001100dw modreg rm 310 310 immediate to registermemory 1000000w mod110 rm data data if w e 1 416 416 immediate to accumulator 0011010w data data if w e 1 34 34 816-bit not e invert registermemory 1111011w mod010 rm 310 310 string manipulation movs e move byteword 1010010w 14 14 cmps e compare byteword 1010011w 22 22 scas e scan byteword 1010111w 15 15 lods e load bytewd to alax 1010110w 12 12 stos e store bytewd fromalax 1010101w 10 10 ins e input bytewd fromdx port 0110110w 14 14 outs e output bytewd to dx port 0110111w 14 14 repeated by count in cx (repreperepzrepnerepnz) movs e move string 11110010 1010010w 8 a 8n 8 a 8n cmps e compare string 1111001z 1010011w 5 a 22n 5 a 22n scas e scan string 1111001z 1010111w 5 a 15n 5 a 15n lods e load string 11110010 1010110w 6 a 11n 6 a 11n stos e store string 11110010 1010101w 6 a 9n 6 a 9n ins e input string 11110010 0110110w 8 a 8n 8 a 8n outs e output string 11110010 0110111w 8 a 8n 8 a 8n control transfer call e call direct within segment 11101000 disp-low disp-high 15 19 registermemory 11111111 mod010 rm 1319 1727 indirect within segment direct intersegment 10011010 segment offset 23 31 segment selector indirect intersegment 11111111 mod011 rm (mod i 11) 38 54 jmp e unconditional jump shortlong 11101011 disp-low 14 14 direct within segment 11101001 disp-low disp-high 14 14 registermemory 11111111 mod100 rm 1117 1121 indirect within segment direct intersegment 11101010 segment offset 14 14 segment selector indirect intersegment 11111111 mod101 rm (mod i 11) 26 34 shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
product name execution timings 54 product name datasheet figure 20. instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles control transfer (continued) ret e returnfrom call within segment 11000011 16 20 within seg adding immed to sp 11000010 data-low data-high 18 22 intersegment 11001011 22 30 intersegment adding immediate to sp 11001010 data-low data-high 25 33 jejz e jump on equalzero 01110100 disp 413 413 jmp not jljnge e jump on lessnot greater or equal 01111100 disp 413 413 takenjmp jlejng e jump on less or equalnot greater 01111110 disp 413 413 taken jbjnae e jump on belownot above or equal 01110010 disp 413 413 jbejna e jump on below or equalnot above 01110110 disp 413 413 jpjpe e jump on parityparity even 01111010 disp 413 413 jo e jump on overflow 01110 000 disp 413 413 js e jumponsign 01111000 disp 413 413 jnejnz e jump on not equalnot zero 01110101 disp 413 413 jnljge e jump on not lessgreater or equal 01111101 disp 413 413 jnlejg e jump on not less or equalgreater 01111111 disp 413 413 jnbjae e jump on not belowabove or equal 01110011 disp 413 413 jnbeja e jump on not below or equalabove 01110111 disp 413 413 jnpjpo e jump on not parpar odd 01111011 disp 413 413 jno e jump on not overflow 01110001 disp 413 413 jns e jumponnotsign 01111001 disp 413 413 jcxz e jump on cx zero 11100011 disp 515 515 loop e loop cx times 11100010 disp 616 616 loop not loopzloope e loop while zeroequal 11100001 disp 616 616 takenloop loopnzloopne e loop while not zeroequal 11100000 disp 616 616 taken enter e enter procedure 11001000 data-low data-high l l e 0 15 19 l e 1 25 29 l l 1 22 a 16(n b 1) 26 a 20(n b 1) leave e leave procedure 11001001 8 8 int e interrupt type specified 11001101 type 47 47 type 3 11001100 45 45 ifintt aken into e interrupt on overflow 11001110 484 484 if int not taken iret e interrupt return 11001111 28 28 bound e detect value out of range 01100010 modreg rm 33C35 33C35 shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers
product name execution timings product name datasheet 55 figure 20. instruction set summary (continued) function format 80c186ea 80c188ea comments clock clock cycles cycles processor control clc e clear carry 11111000 2 2 cmc e complement carry 11110101 2 2 stc e set carry 11111001 2 2 cld e clear direction 11111100 2 2 std e set direction 11111101 2 2 cli e clear interrupt 11111010 2 2 sti e set interrupt 11111011 2 2 hlt e halt 11110100 2 2 wait e wait 10011011 6 6 iftest e 0 lock e bus lock prefix 11110000 2 2 nop e no operation 10010000 3 3 (ttt lll are opcode to processor extension) shaded areas indicate instructions not available in 80868088 microsystems note clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers the effective address (ea) of the memory operand is computed according to the mod and rm fields if mod e 11 then rmis treated as a reg field if mod e 00 then disp e 0 disp-low and disp- high are absent if mod e 01 then disp e disp-low sign-ex- tended to 16-bits disp-high is absent if mod e 10 then disp e disp-high disp-low if rm e 000 then ea e (bx) a (si) a disp if rm e 001 then ea e (bx) a (di) a disp if rm e 010 then ea e (bp) a (si) a disp if rm e 011 then ea e (bp) a (di) a disp if rm e 100 then ea e (si) a disp if rm e 101 then ea e (di) a disp if rm e 110 then ea e (bp) a disp if rm e 111 then ea e (bx) a disp disp follows 2nd byte of instruction (before data if required) except if mod e 00 and rm e 110 then ea e disp-high disp-low ea calculation time is 4 clock cycles for all modes and is included in the execution times given whenev- er appropriate segment override prefix 0 0 1 reg 1 1 0 reg is assigned according to the following segment reg register 00 es 01 cs 10 ss 11 ds reg is assigned according to the following table 16-bit (w e 1) 8-bit (w e 0) 000 ax 000 al 001 cx 001 cl 010 dx 010 dl 011 bx 011 bl 100 sp 100 ah 101 bp 101 ch 110 si 110 dh 111 di 111 bh the physical addresses of all operands addressed by the bp register are computed using the ss seg- ment register the physical addresses of the desti- nation operands of the string primitive operations (those addressed by the di register) are computed using the es segment which may not be overridden
revision history 56 product name datasheet 16.0 revision history intel 80c186ea/80l186ea devices are marked with a 9-character alphanumeric intel fpo number underneath the product number. this data sheet update is valid for devices with an ?a?, ?b?, ?c?, ?d?, or ?e? as the ninth character in the fpo number, as illustrated in figure 3 for the 68-lead plcc package, and as also illustrated in diagrams of the 84-lead qfp (eiaj) package in previous revisions of this datasheet. such devices may also be identified by reading a value of 01h, 02h, 03h from the stepid register. this data sheet replaces the following data sheets: 272019-002?80c186ea 272020-002?80c188ea 272021-002?80l186ea 272022-002?80l188ea 272307-001?sb80c186ea/sb80l186ea 272308-001?sb80c188ea/sb80l188ea 17.0 errata an 80c186ea/80l186ea with a stepid value of 01h or 02h has the following known errata. a device with a stepid of 01h or 02h can be visually identified by noting the presence of an ?a,? ?b?, or ?c? alpha character, next to the fpo number. the fpo number location is shown in figure 3 . 1. an internal condition with the interrupt controller can cause no acknowledge cycle on the inta1 line in response to int1. this errata only occurs when interrupt 1 is configured in cascade mode and a higher priority interrupt exists. this errata will not occur consistently, it is dependent on interrupt timing. an 80c186ea/80l186ea with a stepid value of 03h has no known errata. a device with a stepid of 03h can be visually identified by noting the presence of a ?d? or ?e? alpha character next to the fpo number. the fpo number location is shown in figure 3 .

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